A conventional F-PLL synthesizer will be described with reference to FIGS. 22 and 23 (for example, refer to Patent Document 1 and Non-patent Document 1). FIG. 22 is a diagram showing the configuration of the conventional F-PLL synthesizer. Also, FIG. 23 is a diagram showing the configuration of a fractional control circuit shown in FIG. 22.
Referring to FIG. 22, the conventional F-PLL synthesizer is made up of a reference oscillator (XO) 1 that generates a reference signal Dr(t), a voltage controlled oscillator (VCO) 4 that generates a high frequency signal Do(t), feedback circuits 5 and 6 that generate a feedback signal Dv(t) according to a high frequency signal, a phase comparator (PD) 2 that receives the reference signal and the feedback signal as inputs, and a loop filter (LF) 3 that receives a phase comparison signal De(t) which is an output of the phase comparator 2 as an input, and outputs a control signal Dt(t) of the voltage controlled oscillator 4.
Also, the feedback circuit includes a variable frequency divider (FD) 5 that divides the frequency of a high frequency signal to output the feedback signal, and a fractional control circuit 6 that outputs, to the variable frequency divider 5, the control signal from the frequency divider according to setting data N, K, and M from an external in synchronism with the feedback signal. As shown in FIG. 23, the fractional control circuit 6 includes an adder circuit 11 (11a, 11b, 11c), a delay circuit 12 (12a, 12b), a 1-bit quantization circuit 13, and a multiplier circuit 14.
In the F-PLL synthesizer, the control signal of the frequency division has a cyclic property and fluctuates with a time, and a time average nave of the control signal within one cycle is given by (N+K/M). Accordingly, the output frequency fo of the F-PLL synthesizer is represented by the following Expression (1).fo=fr·nave=fr·(N+K/M)  (1)where fr is a phase comparison frequency, N is an integer portion of the frequency division number of the variable frequency divider 5, and K/M is a fractional portion of the frequency division number of the variable frequency divider 5 (for example, refer to Non-patent Document 1).    Patent Document 1: JP 05-500894 A    Non-patent Document 1: T. A. D. Riley, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis” IEEE Journal of Solid State Circuits, Vol. 28, No. 5, MAY. 1993, pp. 553 to 559